As wireless communication standards evolve to utilize wider bandwidths and higherorder modulation schemes, such as 1024-QAM, careful attention must be placed on the embedded Analog to Digital Converter (ADC). For a modern receiver to meet current IEEE 802.11ax (Wi-Fi 6e) standards, it must be able to transmit a 1024-QAM signal with a bandwidth of 160 MHz. Historically, pipelined architectures have performed well with wide bandwidths and high resolution; however, these pipelined ADC’s have poor power to bandwidth tradeoffs. For mobile devices, power consumption is very limited, and the chosen ADC design has a significant impact on overall battery life. Successive Approximation Register (SAR) ADCs have exceptionally low power con- sumption, but arent able to perform at the desired speeds. Recent works have shown that "Time-Interleaving" several SAR ADCs results in the ability to achieve the de- sired speeds, while consuming much less power than a traditional pipelined ADC. This method utilizes several SAR ADCs in parallel, with each starting its acquisition at a different time. The resulting outputs from each ADC are then "Interleaved" to produce a collective output at a much faster sampling rate. For example, a 10 bit, 500 Msps ADC can be made from 5 "Interleaved" 10 bit SAR ADCs, each having a sample rate of just 100 Msps.