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Abstract
Due to globalization and the shift to the horizontal business model, there areemerging security concerns in the semiconductor industry including FPGAs. Mod- ern FPGAs are system on a chip platforms that integrates a processing system with programmable logic. The horizontal design flow for FPGAs supports third party in- tellectual properties integration into a design. Untrustworthy entities within in the design flow can have several points of attack against the intellectual properties such as intellectual property piracy, reverse engineering, hardware Trojans, and bitstream cloning. Logic locking is a mechanism to design trusted intellectual property, and its distri- bution. Logic locking inserts additional logic into a design with key inputs where the outputs are obfuscated and the design is functional only when a correct key combina- tion is given. Current logic locking schemes hard code the key value into an IP and rely on the assumption that the key will be kept secure during the life cycle of the chip. This work proposes a key update mechanism for logic locked IPs that unlike current schemes, provides dynamically reconfigurable lock updates to the IP and key deployment in a trusted execution environment. We assess the security of the locked IPs and evaluate resource and timing overhead of the proposed scheme. This work demonstrates that the reconfigurable logic locked IP technique is feasible, with results supporting that the locking scheme meets all timing requirements.