In the era of smart technology, IoT technology has been an integral part of the system. IoT systems are susceptible to many type of attacks such as buffer overflow attack and execution flow attacks. Information flow tracking is a technique to monitor the control flow of the program and mitigate the buffer overflow attack.The open source architecture has several applications in design and simulations of security applications such as Common Evaluation Platform(CEP). CEP is a RISC-V based simulation framework for side channel analysis to analyze power traces. These application rely on secure execution, and can have adverse affects if the underlying framework is compromised. Our research focuses on security of RISC-V architecture and its simulation framework of security enabled RISC-V design and simulation to enable hardening the design to be resilient to hardware attacks and capability of run time detection of any attacks. CEP version 1.2 is based on RISC-V ISA, so focus of this thesis is to develop the software simulation model of ISA Level Information Flow Tracking on RISC-V ISA which can be used as a parallel tool to evaluate these new security extension without the need of the hardware to test it. The steps discussed about Assembler modification in this thesis can be used for adding and deploying new instructions within the ISA. An attack setup is developed to manipulate the return address which results in the change of program control flow and also demonstrate the security extensions integrated in the simulation framework to illustrate the security extensions which can detect the attack at run-time.