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Abstract
The semiconductor industry faces a major issue with the rise of counterfeit ICs in the global supply chain. Due to globalisation, the majority of the IC design companies have become fabless. This can be credited to major production costs and the need for highly sophisticated foundries. This horizontal semiconductor supply chain supply model also invites miscreants with malicious intent to enter the supply chain. The attacker may reverse engineer the IC design and reproduce them, a process known as counterfeiting. They may tamper and insert hardware trojans which poses a threat to the integrity of information stored in the IC. To mitigate such attacks, many techniques such as IC camouflaging, Split manufacturing and Logic Encryption have been proposed. This work focuses on Logic Encryption by insertion of key gates. The circuit functions as intended only when the correct key combination is given. These key gates prevent the attacker from obtaining the original circuit. There have been a few attacks proposed recently to decrypt the keys, attacks such as the boolean Satisfiability attack was successful in removing every combinational locking scheme proposed until resilient encryption techniques such as SARLock, TTL lock, Anti-SAT, SFLL were proposed. In this thesis, we create an automated application framework for logic locking and extend its application to FPGA for secure boot. The techniques proposed in this work have been published in [1]. Specifically, the framework consists of an insertion scheme, a test bench generator for both pre and post-insertion netlist, a generalised TCL script template for synthesis and Vivado bitstream generation. This application of Logic Locking adds multiple security layers to an FPGA boot process.