OPTIMIZATION OF COMMUNICATION TRAFFIC IN HAMMER PROTOCOL USING 3D ELECTRONIC MESH NETWORK ON CHIP

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Suresh, H. (2016). OPTIMIZATION OF COMMUNICATION TRAFFIC IN HAMMER PROTOCOL USING 3D ELECTRONIC MESH NETWORK ON CHIP. Unc Charlotte Electronic Theses And Dissertations.
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Abstract

In 1980s a processor had only one core, whose performance was improved by increasing the processor frequency. But this caused overheating and thus improvement in performance was halted. To get more performance multi core processor was introduced that gave better performance. For a chip multiprocessor with hundreds of cores, the cache coherence communication affected the memory access time. The goal of this work is to improve scalability in System on Chip(SoC) multi core processors by using the Hammer cache coherence protocol to maintain cache coherency and reduce the communication traffic by using 3D Mesh Network on Chip as the interconnection network. The GEM5 open source simulator is modified as a part of this thesis to simulate the 3D Mesh NoC. The 3D NoC is observed to produce 11\% reduction in network traffic than the 2D NoC for the Hammer cache coherence protocol and is predicted to provide better performance for higher number of cores and thus improving the scalability of the system. This research is organized into three sections. In the first section, the discussion of different types of cache coherence protocols are discussed and the selection of Hammer protocol for scalability is explained. In the second section, the discussion of various Network on Chips are discussed. In the third section, the implementation in GEM5 and the network algorithm is discussed.

Details
Author

Suresh, Harishankar

Title

OPTIMIZATION OF COMMUNICATION TRAFFIC IN HAMMER PROTOCOL USING 3D ELECTRONIC MESH NETWORK ON CHIP

Physical Description

1 online resource (83 pages) : PDF

Date

2016

Degree Granting Institution

University of North Carolina at Charlotte

Abstract

In 1980s a processor had only one core, whose performance was improved by increasing the processor frequency. But this caused overheating and thus improvement in performance was halted. To get more performance multi core processor was introduced that gave better performance. For a chip multiprocessor with hundreds of cores, the cache coherence communication affected the memory access time. The goal of this work is to improve scalability in System on Chip(SoC) multi core processors by using the Hammer cache coherence protocol to maintain cache coherency and reduce the communication traffic by using 3D Mesh Network on Chip as the interconnection network. The GEM5 open source simulator is modified as a part of this thesis to simulate the 3D Mesh NoC. The 3D NoC is observed to produce 11\% reduction in network traffic than the 2D NoC for the Hammer cache coherence protocol and is predicted to provide better performance for higher number of cores and thus improving the scalability of the system. This research is organized into three sections. In the first section, the discussion of different types of cache coherence protocols are discussed and the selection of Hammer protocol for scalability is explained. In the second section, the discussion of various Network on Chips are discussed. In the third section, the implementation in GEM5 and the network algorithm is discussed.

Genre

masters theses

Subjects--Topics

Electrical engineering
Computer engineering

Degree

M.S.

Keywords

Cache Coherence Protocol
Chip Multiprocessor
gem5
Multi Core Processors
Network on Chip
System on Chip

Subject Area

Electrical Engineering

Advisor(s)

Han, Tao

Committee Members

Nasipuri, Asis
Ravindran, Arun
Han, Tao

Degree Note

Thesis (M.S.)--University of North Carolina at Charlotte, 2016.

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Rights Holder Information

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Identifier

Suresh_uncc_0694N_11131

Permalink

http://hdl.handle.net/20.500.13093/etd:926