Revisiting the Memory Hierarchy in the Many-Core Era: Computation is Cheap, Bandwidth is Everything

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Rajasekhar, Y. (2014). Revisiting the Memory Hierarchy in the Many-Core Era: Computation is Cheap, Bandwidth is Everything. Unc Charlotte Electronic Theses And Dissertations.
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Abstract

Integrated Circuits (ICs) for logic (computation) have dramatically increased in both capacity and speed since their introduction in 1958. However, memory technology has had only modest improvements in speed. Moreover, to increase capacity and lower the cost per bit, main memory is implemented as a separate, external IC. Thus, relative to logic speeds, memory latency is increasing and physical constraints on external pins limits memory bandwidth. The traditional on-chip cache hierarchy has evolved with the sole goal hiding external memory latency for a single-core, sequential processor; essentially giving the illusion of lower latency. Unfortunately, it does so at the expense of IC resources (transistors), energy, power, and memory bandwidth. As the world quickly moves toward multi/many-core architectures, current cache architectures are not aligned with and in fact, are hostile to future priorities.This dissertation questions the allocation of on-chip resources for logic ICs and proposes a novel memory architecture that (a) actively manages the movement of on-chip and off-chip data, (b) creates a flatter memory hierarchy, and (c) emphasizes efficient bandwidth utilization over latency. The results demonstrate that, when combined with a suitable programming environment, the proposed memory subsystem enables a larger fraction of chip resources to be dedicated to computation. This yields a higher degree of parallelism and ultimately reduces the time-to-completion of an application independent of how fast individual tasks execute.

Details
Author

Rajasekhar, Yamuna

Title

Revisiting the Memory Hierarchy in the Many-Core Era: Computation is Cheap, Bandwidth is Everything

Physical Description

1 online resource (93 pages) : PDF

Date

2014

Degree Granting Institution

University of North Carolina at Charlotte

Abstract

Integrated Circuits (ICs) for logic (computation) have dramatically increased in both capacity and speed since their introduction in 1958. However, memory technology has had only modest improvements in speed. Moreover, to increase capacity and lower the cost per bit, main memory is implemented as a separate, external IC. Thus, relative to logic speeds, memory latency is increasing and physical constraints on external pins limits memory bandwidth. The traditional on-chip cache hierarchy has evolved with the sole goal hiding external memory latency for a single-core, sequential processor; essentially giving the illusion of lower latency. Unfortunately, it does so at the expense of IC resources (transistors), energy, power, and memory bandwidth. As the world quickly moves toward multi/many-core architectures, current cache architectures are not aligned with and in fact, are hostile to future priorities.This dissertation questions the allocation of on-chip resources for logic ICs and proposes a novel memory architecture that (a) actively manages the movement of on-chip and off-chip data, (b) creates a flatter memory hierarchy, and (c) emphasizes efficient bandwidth utilization over latency. The results demonstrate that, when combined with a suitable programming environment, the proposed memory subsystem enables a larger fraction of chip resources to be dedicated to computation. This yields a higher degree of parallelism and ultimately reduces the time-to-completion of an application independent of how fast individual tasks execute.

Genre

doctoral dissertations

Subjects--Topics

Computer engineering

Degree

Ph.D.

Keywords

FPGAs
Many-Core
Memory Subsystem
Reconfigurable Computing

Subject Area

Electrical Engineering

Advisor(s)

Sass, Ron

Committee Members

Conrad, James
Joshi, Bharat
Yang, Jing

Degree Note

Thesis (Ph.D.)--University of North Carolina at Charlotte, 2014.

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Rights Holder Information

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Identifier

Rajasekhar_uncc_0694D_10683

Permalink

http://hdl.handle.net/20.500.13093/etd:548