Productively scaling hardware designs over increasing resources using a systematic design analysis approach

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Schmidt, A. (2011). Productively scaling hardware designs over increasing resources using a systematic design analysis approach. Unc Charlotte Electronic Theses And Dissertations.
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Abstract

As processor development shifts from strict single core frequency scaling to het- erogeneous resource scaling two important considerations require evaluation. First, how to design systems with an increasing amount of heterogeneous resources, and second, how to maintain a designer's productivity as the number of possible con- figurations grows. Therefore, it is necessary to determine what useful information can be gathered from existing designs to help predict or identify a design's potential scalability, as well as, identifying which routine tasks can be automated to improve a designer's productivity. Moreover, once this information is collected, how can this information be conveyed to the designer such that it can be used to increase overall productivity when implementing the design over increasing amounts of resources?This research looks at various approaches to analyze designs and attempts to distribute an application efficiently across a heterogeneous cluster of computing re- sources through the use of a Systematic Design Analysis flow and an assortment of productivity tools. These tools provide the designer with projections on the amount of resources needed to scale an existing design to a specified performance, as well as, projecting the performance based on a specified amount of resources. This is accomplished through the combination of static HDL profiling, component synthesis resource utilization, and runtime performance monitoring. For evaluation, four case studies are presented to demonstrate the proposed flow's scalability on a small scale cluster of FPGAs. The results are highly favorable, providing orders of magnitude speedup with minimal intervention from the designer.

Details
Author

Schmidt, Andrew

Title

Productively scaling hardware designs over increasing resources using a systematic design analysis approach

Physical Description

1 online resource (248 pages) : PDF

Date

2011

Degree Granting Institution

University of North Carolina at Charlotte

Abstract

As processor development shifts from strict single core frequency scaling to het- erogeneous resource scaling two important considerations require evaluation. First, how to design systems with an increasing amount of heterogeneous resources, and second, how to maintain a designer's productivity as the number of possible con- figurations grows. Therefore, it is necessary to determine what useful information can be gathered from existing designs to help predict or identify a design's potential scalability, as well as, identifying which routine tasks can be automated to improve a designer's productivity. Moreover, once this information is collected, how can this information be conveyed to the designer such that it can be used to increase overall productivity when implementing the design over increasing amounts of resources?This research looks at various approaches to analyze designs and attempts to distribute an application efficiently across a heterogeneous cluster of computing re- sources through the use of a Systematic Design Analysis flow and an assortment of productivity tools. These tools provide the designer with projections on the amount of resources needed to scale an existing design to a specified performance, as well as, projecting the performance based on a specified amount of resources. This is accomplished through the combination of static HDL profiling, component synthesis resource utilization, and runtime performance monitoring. For evaluation, four case studies are presented to demonstrate the proposed flow's scalability on a small scale cluster of FPGAs. The results are highly favorable, providing orders of magnitude speedup with minimal intervention from the designer.

Genre

doctoral dissertations

Subjects--Topics

Electrical engineering
Computer engineering

Degree

Ph.D.

Keywords

Field Programmable Gate Arrays
High Performance Computing
Performance Monitoring
Productivity
Reconfigurable Computing
Systematic Design Analysis

Subject Area

Electrical Engineering

Advisor(s)

Sass, Ronald

Committee Members

Conrad, James
Joshi, Bharat
Adams, Ryan
Schlueter, Shannon

Degree Note

Thesis (Ph.D.)--University of North Carolina at Charlotte, 2011.

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Rights Holder Information

Copyright is held by the author unless otherwise indicated.

Identifier

Schmidt_uncc_0694D_10208

Permalink

http://hdl.handle.net/20.500.13093/etd:340