As the memory wall becomes an obstacle in the multi-core architecture, many hardware solutions have been proposed to utilize the available memory bandwidth more efficiently. One such implementation uses a B-tree based controller implemented in hardware to manage a memory subsystem. This thesis investigates various design factors and design decisions to implement the B-tree controller purely in software running on a generic soft-core or a hard-core processor. It investigates why software is slower and what factors if changed, can make it a feasible solution, it at all, and finally present an environment in which software can become competitive to hardware.
